The present invention relates to an received-signal absolute phasing apparatus of receiver, particularly to a received-signal absolute phasing apparatus of receiver, which makes the following coincide with the transmission side: signal point arrangements of received I and Q base-band signals of two series obtained by receiving and demodulating: a signal to be PSK-modulated in which at least an 8PSK-modulated digital signal among 8PSK-modulated digital signal, QPSK-modulated digital signal, and BPSK-modulated digital signal are time-multiplexed with a BPSK-modulated frame synchronizing signal, by a hierarchical transmission system; or a signal to be PSK-modulated in which at least 8PSK-modulated digital signal and QPSK-modulated digital signal among 8PSK-modulated digital signal, QPSK-modulated digital signal, and BPSK-modulated digital signal are time-multiplexed with a BPSK-modulated frame synchronizing signal, by the system.
Practical use of digital satellite TV broadcasting is advanced which uses a plurality of modulation systems different from each other in required C/N such as a hierarchical transmission system for repeatedly transmitting a wave to be 8PSK-modulated, a wave to be QPSK-modulated, and a wave to be BPSK-modulated by time-multiplexing the waves.
FIG. 11A is an illustration showing a frame configuration of a hierarchical transmission system. One frame is configured by a frame synchronizing signal pattern comprising 32 BPSK-modulated symbols (among 32 symbols, 20 latter-half symbols are actually used as a frame synchronizing signal), a TMCC (Transmission and Multiplexing Configuration Control) pattern for identifying a transmission multiplexing configuration comprising 128 BPSK-modulated symbols, a super-frame-identifying signal pattern comprising 32 symbols (among 32 symbols, 20 latter-half symbols are actually used as a super-frame-identifying signal), main signal of 203 8PSK(trellis-CODEC-8PSK)-modulated symbols, burst symbol signal (BS) of 4 symbols obtained by BPSK-modulating a pseudo random-noise (PN) signal, main signal of 203 8PSK(trellis-CODEC-8PSK)-modulated symbols, burst symbol signal (BS) of 4 symbols obtained by BPSK-modulating a pseudo random-noise (PN) signal, . . . , main signal of 203 QPSK-modulated symbols, burst symbol signal (BS) of 4 symbols obtained by BPSK-modulating a pseudo random-noise (PN) signal, main signal of 203 QPSK-modulated symbols, and burst symbol signal (BS) of 4 BPSK-modulated symbols in order.
In case of a receiver for receiving digital waves to be modulated (waves to be PSK-modulated) according to the hierarchical transmission system, an intermediate-frequency signal of a received signal received by a receiving circuit is demodulated by a demodulating circuit and I and Q base-band signals of two series showing instantaneous values of I axis and Q axis orthogonal to each other every symbol (hereafter, I and Q base-band signals are also referred to as I and Q symbol stream data values) are obtained. By acquiring a frame synchronizing signal from the demodulated I an Q base-band signals, obtaining a present received-signal-phase rotation angle from the signal point arrangement of the acquired frame synchronizing signal, and antiphase-rotating the demodulated I and Q base-band signals in accordance with the obtained received-signal-phase rotation angle, absolute phase generation for adjusting the I and Q base-band signals to a transmission-signal phase angle is performed by an absolute-angle-generating circuit.
As shown in FIG. 12, an absolute-phase generating circuit of a receiver for receiving waves to be PSK-modulated according to a conventional hierarchical transmission system is configured by a frame sync detecting/regenerating circuit 2 serving as frame sync acquiring means provided for the output side of a demodulating circuit 1 to acquire a frame synchronizing signal, a remapper 7 serving as antiphase rotating means comprising a ROM, and received-signal-phase rotation angle detecting circuit 8 serving as received-signal-phase rotation angle detecting means. Symbol 9 denotes a transmission-configuration identifying circuit for identifying a transmission multiplexing configuration shown in FIG. 11A, which outputs a 2-bit-modulating-system identifying signal DM.
The demodulating circuit 1 obtains I and Q base-band signals by quadrature-detecting an intermediate frequency signal IF. In the demodulating circuit 1, symbol 10 denotes a carrier-wave regenerating circuit for regenerating two reference carrier waves fc1 (=cos xcfx89t) and fc2 (=sin xcfx89t) whose frequencies and phases synchronize with a received carrier wave and which is orthogonal to each other because their phase are shifted by 90xc2x0 from each other, 60 and 61 denote multipliers for multiplying the intermediate frequency signal IF by fc1 and fc2, 62 and 63 denote A/D converters for A/D-converting outputs of the multipliers 60 and 61 at a sampling rate two times larger than a symbol rate, 64 and 65 denote digital filters for performing band restriction to outputs of the A/D converters 62 and 63 through digital signal processing, and 66 and 67 denote thinning circuits for thinning outputs of the digital filters 64 and 65 at a xc2xd sampling rate and outputting I and Q base-band signals (I and Q symbol stream data values) of two series showing instantaneous values of I-axis and Q-axis every symbol. The thinning circuits 66 and 67 transmit I and Q base-band signals I(8) and Q(8) (a numeral in parentheses shows the number of quantization bits and is hereafter also simply referred to as I and Q by omitting the number of quantization bits) having 8 quantization bits (two""s complement system).
Mapping for each modulation system at the transmission side will be described below by referring to FIGS. 13A-13C. FIG.13A shows signal point arrangements on an I-Q phase plane (also referred to as I-Q vector plane or I-Q signal space diagram) using 8PSK for a modulation system. The 8PSK modulation system makes it possible to transmit a 3-bit digital signal (abc) by one symbol. Combination of bits configuring one symbol includes eight ways such as (000), (001), (010), (011), (100), (101), (110), and (111). These 3-bit digital signals are converted into signal point arrangements xe2x80x9c0xe2x80x9d to xe2x80x9c7xe2x80x9d on the transmission-side I-Q phase plane in FIG. 13A and this conversion is referred to as 8PSK mapping.
In case of the example shown in FIG. 13A, the bit string (000) is converted into a signal point arrangement xe2x80x9c0xe2x80x9d, the bit string (001) into a signal point arrangement xe2x80x9c1xe2x80x9d, the bit string (011) into a signal point arrangement xe2x80x9c2xe2x80x9d, the bit string (010) into a signal point arrangement xe2x80x9c3xe2x80x9d, the bit string (100) into a signal point arrangement xe2x80x9c4xe2x80x9d, the bit string (101) into a signal point arrangement xe2x80x9c5xe2x80x9d, the bit string (111) into a signal point arrangement xe2x80x9c6xe2x80x9d, and the bit string (110) into a signal point arrangement xe2x80x9c7xe2x80x9d.
FIG. 13B shows signal point arrangements on an I-Q phase plane at the time of using QPSK for a modulation system. The QPSK modulation system makes it possible to transmit a 2-bit digital signal (de) by one symbol. Combination of bits configuring the symbol includes four ways such as (00), (01), (10), and (11). In case of the example in FIG. 13B, the bit string (00) is converted into a signal point arrangement xe2x80x9c1xe2x80x9d, the bit string (01) into a signal point arrangement xe2x80x9c3xe2x80x9d, the bit string (11) into a signal point arrangement xe2x80x9c5xe2x80x9d, and the bit string (10) into a signal point arrangement xe2x80x9c7xe2x80x9d.
FIG. 13C shows signal point arrangements at the time of using BPSK for a modulation system. The BPSK modulation system transmits a 1-bit signal (f) by one symbol. In case of the digital signal (f), bit (0) is converted into a signal point arrangement xe2x80x9c0xe2x80x9d and bit (1) is converted into a signal point arrangement xe2x80x9c4xe2x80x9d. Relations between signal point arrangements and arrangement numbers of modulation systems are the same each other on the basis of 8BPSK.
I axis and Q axis of QPSK and BPSK in the hierarchical transmission system coincide with I axis and Q axis of 8PSK.
When the phase of a received carrier wave coincides with the phase of the reference carrier wave fc1 or fc2 regenerated by the carrier-wave regenerating circuit 10, the phase of the received-signal point on the I-Q phase plane according to I and Q base-band signals I(8) and Q(8) at the reception side at the time of receiving digital signals corresponding to signal point arrangements xe2x80x9c0xe2x80x9d to xe2x80x9c7xe2x80x9d on the I-Q phase plane at the transmission side coincide with those of the transmission side. Therefore, by directly using the relations between signal point arrangements and digital signals at the transmission side (refer to FIGS. 13A-13C), it is possible to correctly identify a digital signal received from a signal point arrangement of a received-signal point.
In fact, however, the reference carrier wave fc1 or fc2 can take various phase states for a received carrier wave. Therefore, a received-signal point at the reception side is located at a phase position rotated by a certain angle xcex8 from the transmission side. Moreover, when a phase of a received carrier wave fluctuates, xcex8 also fluctuates. When the phase of the received signal point rotates from the transmission side at random, it becomes impossible to identify a received digital signal. For example, when xcex8 is equal to xcfx80/8, the received-signal point of the digital signal (000) of the signal point arrangement xe2x80x9c0xe2x80x9d in the 8PSK modulation system at the transmission side is located between the signal point arrangements xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d at the reception side. Therefore, at the time of assuming that the digital signal (000) is received at the signal point arrangement xe2x80x9c0xe2x80x9d, it is judged that the signal (000) is correctly received. However, at the time of assuming that the digital signal (000) is received at the signal point arrangement xe2x80x9c1xe2x80x9d, it is erroneously judged that the digital signal (001) is received. Therefore, for a received-signal point to keep a certain rotation angle from the transmission side, the carrier-wave regenerating circuit 10 corrects phases of the reference carrier waves fc1 and fc2 so that a digital signal can be correctly identified.
Specifically, by making a VCO (voltage control oscillator) 11 of the carrier-wave regenerating circuit 10 oscillate at a transmission carrier wave frequency, the reference carrier wave fc1 is generated and moreover, the reference carrier wave fc2 is generated by advancing a phase of an oscillation signal of the VCO 11 by 90xc2x0 by a 90xc2x0 phase shifter 12. Then, by changing control voltages of the VCO 11, phases of the reference carrier wave fc1 or fc2 can be changed.
The carrier-wave regenerating circuit 10 is provided with phase error tables 13, 14-1 and 14-2, and 15-1 to 15-4 respectively configured by a ROM and formed by tabulating relations between various data sets of the I and Q base-band signals I(8) and Q(8) and carrier-wave phase error data having 8 quantization bits (two""s complement system) (hereafter also simply referred to as phase error data) xcex94xcfx86(8) (refer to FIG. 14) by modulation systems of 8PSK, QPSK and BPSK. The I and Q base-band signals I(8) and Q(8) are input to the phase error tables 13, 14-1 and 14-2, and 15-1 to 15-4 in parallel. A phase error table selectively enabled by a selector to be described later outputs the phase error data xcex94xcfx86(8) corresponding to the I and Q base-band signals I(8) and Q(8) input from the demodulating circuit 1.
The phase error table 13 is used for 8PSK, in which the relation between a phase angle xcfx86 (refer to FIG. 15) on the I-Q phase plane of the received-signal point shown by the I and Q base-band signals I(8) and Q(8) input from the demodulating circuit 1 and the phase error data xcex94xcfx86(8) is configured as shown in FIG. 17. A selector 16 enables only the phase error table 13 (makes only the phase error table 13 active) while the demodulating circuit 1 demodulates digital waves to be modulated in accordance with the BPSK modulation system (specified by a modulation-system identifying signal DM supplied from a transmission-configuration identifying circuit 9 to be described later) in accordance with a clock CLKSYB (refer to FIG. 11B) having a symbol rate synchronous with outputs of the I and Q base-band signals I(8) and Q(8) supplied from the demodulating circuit 1 and reads the phase error data xcex94xcfx86(8) corresponding to the set data of the I(8) and Q(8) whenever the demodulating circuit 1 outputs the I and Q base-band signals I(8) and Q(8) for one symbol. The phase error data xcex94xcfx86(8) is converted into a phase error voltage by a D/A converter 17 and thereafter, low-frequency components are fetched from the phase error voltage by an LPF 18 and the voltage is applied to the VCO 11 as a control voltage. When the phase error data xcex94xcfx86(8) is equal to 0, outputs of the LPF 18 are not changed or phases of the reference carrier wave fc1 or fc2 are not changed. However, when the phase error data xcex94xcfx86(8) is positive, outputs of the LPF 18 increase and phases of the reference carrier waves fc1 and fc2 are delayed. However, when the phase error data xcex94xcfx86(8) is negative, outputs of the LPF 18 decrease and phases of the reference carrier waves fc1 and fc2 are advanced.
In the phase error table 13, the difference between xcfx86 and the phase of the nearest one of the signal point arrangements xe2x80x9c0xe2x80x9d to xe2x80x9c7xe2x80x9d serves as the phase error data xcex94xcfx86(8). Therefore, positions of digital signals of signal point arrangements of 0, xcfx80/4, 2xcfx80/4, 3xcfx80/4, 4xcfx80/4, 5xcfx80/4, 6xcfx80/4, and 7xcfx80/4 according to the 8PSK modulation system at the transmission side are respectively corrected to a position rotated by "THgr"=mxc3x97xcfx80/4 (m=one of integers 0 to 7: refer to FIG. 16) on the I-Q phase plane at the reception side. Symbol "THgr" denotes a received-signal phase rotation angle. Thereby, because received-signal points according to the 8PSK modulation system are brought to positions of phases 0, xcfx80/4, 2xcfx80/4, 3xcfx80/4, 4xcfx80/4, 5xcfx80/4, 6xcfx80/4, and 7xcfx80/4, it is possible to assign the signal point arrangements xe2x80x9c0xe2x80x9d to xe2x80x9c7xe2x80x9d on the I-Q phase plane at the reception side to the same phases as that of the transmission side (However, the relation between a signal point arrangement and a digital signal is changed in accordance with "THgr".). By detecting "THgr" and antiphase-rotating it by xe2x88x92"THgr", it is possible to make the relation between a signal point arrangement and a digital signal same as that of the transmission side (absolute phase generation) and easily identify a received digital signal.
The phase error tables 14-1 and 14-2 are used for QPSK and the relation between phase angle xcfx86 and phase error data xcex94xcfx86(8) on the I-Q phase plane of the received-signal point shown by the I and Q base-band signals I(8) and Q(8) is configured as shown in FIGS. 18 and 19. Under normal reception, the selector 16 enables only the phase error table 14-1 when the received-signal phase rotation angle "THgr" is equal to 0, 2xcfx80/4, 4xcfx80/4, or 6xcfx80/4 while the demodulating circuit 1 demodulates digital waves to be modulated according to the OPSK modulation system in accordance with a clock CLKSYB having a symbol rate and reads the phase error data xcex94xcfx86(8) corresponding to the set data for I and Q base-band signals I(8) and Q(8) for one symbol out of the phase error table 14-1 whenever the demodulating circuit 1 outputs the I and Q base-band signals I(8) and Q(8).
In the phase error table 14-1, the difference between xcfx86 and the phase of the nearest one of the signal point arrangements xe2x80x9c1xe2x80x9d, xe2x80x9c3xe2x80x9d, xe2x80x9c5xe2x80x9d, and xe2x80x9c7xe2x80x9d serves as the phase error data xcex94xcfx86. Therefore, positions of digital signals of the signal point arrangements xe2x80x9c1xe2x80x9d, xe2x80x9c3xe2x80x9d, xe2x80x9c5xe2x80x9d, and xe2x80x9c7xe2x80x9d of the phases xcfx80/4, 3xcfx80/4, 5xcfx80/4, and 7xcfx80/4 according to the QPSK modulation system at the transmission side are respectively corrected to a position rotated by "THgr" on the I-Q phase plane at the reception side. When "THgr" is equal to 0, 2xcfx80/4, 4xcfx80/4, or 6xcfx80/4, a received-signal point according to the QPSK modulation system is brought to a position of xcfx80/4, 3xcfx80/4, 5xcfx80/4, or 7xcfx80/4. By detecting "THgr" and antiphase-rotating it by xe2x88x92"THgr", it is possible to make the relation between a signal point arrangement and a digital signal same as that of the transmission side (absolute phase generation) and easily identify a received digital signal.
Moreover, the selector 16 enables only the phase error table 14-2 when "THgr" is equal to xcfx80/4, 3xcfx80/4, 5xcfx80/4, or 7xcfx80/4 while the demodulating circuit 10 demodulates digital waves to be modulated according to the QPSK modulation system and reads the phase error data xcex94xcfx86(8) corresponding to the set data of the I and Q base-band signals I(8) and Q(8) for one symbol out of the phase error table 14-2 whenever the demodulating circuit 1 outputs the I and Q base-band signals I(8) and Q(8).
In the phase error table 14-2, the difference between f and the phase of the nearest one of the signal point arrangements xe2x80x9c0xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c4xe2x80x9d, and xe2x80x9c6xe2x80x9d serves as the phase error data xcex94xcfx86. Therefore, positions of digital signals of the signal point arrangements xe2x80x9c1xe2x80x9d, xe2x80x9c3xe2x80x9d, xe2x80x9c5xe2x80x9d, and xe2x80x9c7xe2x80x9d of the phases xcfx80/4, 3xcfx80/4, 5xcfx80/4, and 7xcfx80/4 according to the QPSK modulation system at the transmission side are respectively corrected to a position rotated by the above "THgr". When "THgr" is equal to xcfx80/4, 3xcfx80/4, 5xcfx80/4, or 7xcfx80/4, a received-signal point according to the QPSK modulation system is brought to the position of the phase "THgr", 2xcfx80/4, 4xcfx80/4, or 6xcfx80/4. By detecting "THgr" and antiphase-rotating it by xe2x88x92"THgr", it is possible to obtain the same phase as that of the transmission side (absolute phase generation), make the relation between a signal point arrangement and a digital signal same as that of the transmission side, and easily identify a received digital signal.
The phase error tables 15-1 to 15-4 are used for BPSK and the relation between the phase angle xcfx86 and the phase error data xcex94xcfx86(8) on the I-Q phase plane of the received-signal point shown by the I and Q base-band signals I(8) and Q(8) is configured as shown in FIGS. 20 to 23. Selector 16 enables only the phase error table 14-1 when the received-signal phase rotation angle "THgr" is equal to 0 or 4xcfx80/4 while the demodulating circuit 1 demodulates digital waves to be modulated according to the BPSK modulation system synchronously with a clock CLKSYB having a symbol rate and reads the phase error data xcex94xcfx86(8) corresponding to the set data for the I and Q base-band signals I(8) and Q(8) for one symbol out of the phase error table 15-1 whenever the demodulating circuit 1 outputs the base band signals I(8) and Q(8).
In the phase error table 15-1, the difference between xcfx86 and the phase of the nearest one of the signal point arrangements xe2x80x9c0xe2x80x9d and xe2x80x9c4xe2x80x9d serves as the phase error data xcex94xcfx86. Therefore, positions of digital signals of the signal point arrangements xe2x80x9c0xe2x80x9d and xe2x80x9c4xe2x80x9d of the phases 0 and 4xcfx80/4 according to the BPSK modulation system at the transmission side are respectively corrected to a position rotated by the above "THgr" on the I-Q phase plane at the reception side. When "THgr" is equal to 0 or 4xcfx80/4, a received-signal point according to the BPSK modulation system is brought to the position of the phase 0 or 4xcfx80/4.
Moreover, the selector 16 enables only the phase error table 15-2 when "THgr" is equal to xcfx80/4 or 5xcfx80/4 while digital waves to be modulated are demodulated in accordance with the BPSK modulation system and reads the phase error data xcex94xcfx86(8) corresponding to the set data for the I and Q base-band signals I(8) and Q(8) for one symbol out of the phase error table 15-2 whenever the demodulating circuit 1 outputs the I and Q base-band signals I(8) and Q(8).
In the phase error table 15-2, the difference between xcfx86 and the phase of the nearest one of the signal point arrangements xe2x80x9c1xe2x80x9d and xe2x80x9c5xe2x80x9d serves as the phase error data xcex94xcfx86. Therefore, positions of digital signals of the signal point arrangements xe2x80x9c0xe2x80x9d and xe2x80x9c4xe2x80x9d of the phases 0 and 4xcfx80/4 according to the BPSK modulation system at the transmission side are respectively corrected to a position rotated by the above "THgr" on the I-Q phase plane at the reception side. When "THgr" is equal to xcfx80/4 or 5xcfx80/4, a received-signal point according to the BPSK modulation system is brought to the position of the phase xcfx80/4 or 5xcfx80/4.
Moreover, the selector 16 enables only the phase error table 15-3 when "THgr" is equal to 2xcfx80/4 or 6xcfx80/4 while demodulating digital waves to be modulated in accordance with the BPSK modulation system and reads the phase error data xcex94xcfx86(8) corresponding to the set data for the I and Q base-band signals I(8) and Q(8) for one symbol from the phase error table 15-3 whenever the demodulating circuit 1 outputs the I(8) and Q(8).
In the phase error table 15-3, the difference between xcfx86 and the phase of the nearest one of the signal point arrangements xe2x80x9c2xe2x80x9d and xe2x80x9c6xe2x80x9d serves as the phase error data xcex94xcfx86. Therefore, positions of digital signals of the signal point arrangements xe2x80x9c0xe2x80x9d and xe2x80x9c4xe2x80x9d of the phases 0 and 4xcfx80/4 according to the BPSK modulation system at the transmission side are respectively corrected to a position rotated by the above "THgr" on the I-Q phase plane at the reception side. When "THgr" is equal to 2xcfx80/4 or 6xcfx80/4, a received-signal point according to the BPSK modulation system is brought to the position of the phase 2xcfx80/4 or 6xcfx80/4.
Moreover, the selector 16 enables only the phase error table 15-4 when "THgr" is equal to 3xcfx80/4 or 7xcfx80/4 while demodulating digital waves to be modulated according to the BPSK modulation system and reads the phase error data xcex94xcfx86(8) corresponding to the set data for the I and Q base-band signals I(8) and Q(8) for one symbol out of the phase error table 15-4 whenever the demodulating circuit 1 outputs the I(8) and Q(8).
In the phase error table 15-4, the difference between xcfx86 and the phase of the nearest one of the signal point arrangements xe2x80x9c3xe2x80x9d and xe2x80x9c7xe2x80x9d serves as the phase error data xcex94xcfx86. Therefore, positions of digital signals of the signal point arrangements xe2x80x9c0xe2x80x9d and xe2x80x9c4xe2x80x9d of the phases 0 and 4xcfx80/4 according to the BPSK modulation system at the transmission side are respectively corrected to a position rotated by the above E) on the I-Q phase plane at the reception side. When "THgr" is equal to 3xcfx80/4 or 7xcfx80/4, a received-signal point according to the BPSK modulation system is brought to the position of the phase 3xcfx80/4 or 7xcfx80/4. Also in the case of BPSK modulation, by detecting "THgr" and antiphase-rotating it by xe2x88x92"THgr", it is possible to obtain the same phase as that of the transmission side (absolute phase generation), make the relation between a signal point arrangement and a digital signal same as that of the transmission side, and easily identify a received digital signal.
As shown in FIG. 24, the frame sync detecting/regenerating circuit 2 is configured by a BPSK demapper 3, sync detecting circuits 40 to 47, a frame synchronizing circuit 5, an OR gate circuit 53, and a frame-synchronizing-signal generator 6. The received-signal-phase rotation angle detecting circuit 8 is configured by delay circuits 81 and 82, a 0xc2x0/180xc2x0 phase rotating circuit 83, averaging circuits 85 and 86, and a received-phase judging circuit 87.
The I and Q base-band signals I(8) and Q(8) output from the demodulating circuit 1 are input to a BPSK demapper section 3 of the frame sync detecting/regenerating circuit 2 in order to acquire, for example, a BPSK-modulated frame synchronizing signal and a BPSK-demapped bit stream B0 is output. The BPSK demapper section 3 is configured by, for example, a ROM.
Then, a frame-synchronizing signal will be described below. In case of the hierarchical transmission system, a frame synchronizing signal is BPS-modulated at a required lowest C/N and transmitted. A frame synchronizing signal configured by 20 bits has a bit stream of (S0S1 . . . S18S19)=(11101100110100101000) which are transmitted in order starting with S0. A bit stream of a frame-synchronizing signal is also referred to as xe2x80x9cSYNCPATxe2x80x9d. The bit stream is converted into the signal point arrangement xe2x80x9c0xe2x80x9d or xe2x80x9c4xe2x80x9d through the BPSK mapping shown in FIG. 13C at the transmission side and a converted symbol stream is transmitted.
To acquire BPSK-modulated and transmitted 20 bits, that is, a frame synchronizing signal of 20 symbols, it is necessary to convert a received symbol into a bit through the BPSK demapping shown in FIG. 25A inversely to the mapping converted at the transmission side. Therefore, as shown in FIG. 25A, a demodulated signal is judged as (0) when the signal is received in the hatched area on the I-Q phase plane at the reception side and the signal is judged as (1) when it is received in the not-hatched area. That is, an output is classified into (0) or (1) depending on the fact that the output is received in which area of two judgment areas divided by a BPSK judging borderline shown by a bold line in FIG. 25A and thereby, it is assumed that BPSK demapping is performed.
The I and Q base-band signals I(8) and Q(8) are input to the BPSK demapper section 3 in order to undergo the BPSK demapping and a bit stream B0 BPSK-demapped in the BPSK demapper section 3 is output. In this specification, a demapper denotes a circuit for performing demapping. The bit stream B0 is input to the sync detecting circuit 40 in which a bit stream of a frame-synchronizing signal is acquired from the bit stream B0.
Then, the sync detecting circuit 40 will be described below by referring to FIG. 26. The sync detecting circuit 40 has 20 D-flip-flops (hereafter referred to as D-F/Fs) D19 to D0 connected in series and a 20-stage shift register is configured by these D-F/Fs D19 to D0. The bit stream B0 is input to the D-F/F D19 and successively shifted up until D-F/F D0 and at the same time, logic inversion is applied to predetermined bits of outputs of the D-F/F D19 to D-F/F D0 and then, the outputs are input to an AND gate 51. In the AND gate 51, when output states (D0D1 . . . D18D19) of the D-F/F D19 to D0 are set to (11101100110100101000), an output SYNA0 of the AND gate 51 becomes a high potential. That is, when a SYNCPAT is acquired, the SYNA0 becomes a high potential.
The output SYNA0 of the sync detecting circuit 40 is input to the frame synchronizing circuit 5 through the OR gate circuit 53. In the frame synchronizing circuit 5, it is judged that frame sync is effectuated when it is confirmed that an output SYA of the OR gate circuit 53 repeatedly becomes a high potential every certain frame cycle and a frame synchronizing pulse is output every frame cycle.
Usually, in case of a hierarchical transmission system to which a plurality of modulation systems having necessary C/Ns different from each other are time-multiplexed and repeatedly transmitted every frame, header data values showing their multiple configurations are multiplexed (TMCC pattern in FIG. 11A). The transmission-configuration identifying circuit 9 extracts TMCC showing a multiple configuration from a bit stream after BPSK demapper input from the frame synchronizing circuit 5 after it is judged by the frame sync detecting/regenerating circuit 2 that frame sync is effectuated, decodes the TMCC, and outputs a modulation-system identifying signal DM showing by which modulation system the present I and Q base-band signals I and Q are generated to the selector 16 (refer to FIG. 11B). Moreover, the received-signal phase rotation angle detecting circuit 8 detects a received-signal phase rotation angle "THgr" in accordance with a regenerated-frame synchronizing signal output from the frame-synchronizing-signal generator 6 after it is judged by the frame sync detecting/regenerating circuit 2 that frame sync is effectuated and outputs a 3-bit received-signal phase rotation angle signal AR(3) to the remapper 7 and the selector 16 of the carrier wave regenerating circuit 10.
The selector 16 of the carrier wave regenerating circuit 10 reads the phase error data xcex94xcfx86(8) from a phase error table corresponding to a modulation system and the received-signal phase rotation angle "THgr" after the modulation system identifying signal DM is input from the transmission configuration identifying circuit 9 and moreover, the received-signal phase rotation angle signal AR(3) is input from the received-signal phase rotation angle detecting circuit 8 and outputs the phase error data xcex94xcfx86(8) to the D/A converter 17. Until then, however, the selector 16 reads the phase error data xcex94xcfx86(8) out of the phase error table 13 for 8PSK.
Thus, until the transmission configuration identifying circuit 9 identifies a multiple configuration and the received-signal phase rotation angle detecting circuit 8 detects the received-signal phase rotation angle "THgr", the demodulating circuit 1 always operates as an 8PSK demodulating circuit. Therefore, a received-signal point rotates by "THgr"=mxc3x97xcfx80/4 (m is one of integers 0 to 7) from the transmission side depending on a phase state of the reference carrier wave fc1 or fc2 regenerated by the carrier wave regenerating circuit 10 of the demodulating circuit 1.
That is, as shown in FIG. 13C, a received-signal point of a symbol stream of a frame synchronizing signal BPSK-mapped to the signal point arrangement xe2x80x9c0xe2x80x9d for the bit (0) or BPSK-mapped to the signal point arrangement xe2x80x9c4xe2x80x9d for the bit (1) at the transmission side appears on one of the following cases depending on a phase state of the reference carrier wave fc1 or fc2: the signal point arrangement xe2x80x9c0xe2x80x9d or xe2x80x9c4xe2x80x9d where "THgr" equals 0 similarly to the case of the transmission side, signal point arrangement xe2x80x9c1xe2x80x9d or xe2x80x9c5xe2x80x9d rotated by "THgr"=xcfx80/4 phases, signal point arrangement xe2x80x9c2xe2x80x9d or xe2x80x9c6xe2x80x9d rotated by "THgr"=2xcfx80/4 phases, the signal point arrangement xe2x80x9c3xe2x80x9d or xe2x80x9c7xe2x80x9d rotated by "THgr"=3xcfx80/4 phases, signal point arrangement xe2x80x9c4xe2x80x9d or xe2x80x9c0xe2x80x9d rotated by "THgr"=4xcfx80/4 phases, signal point arrangement xe2x80x9c5xe2x80x9d or xe2x80x9c1xe2x80x9d rotated by "THgr"=5xcfx80/4 phases, signal point arrangement xe2x80x9c6xe2x80x9d or xe2x80x9c2xe2x80x9d rotated by "THgr"=6xcfx80/4 phases, and signal point arrangement xe2x80x9c7xe2x80x9d or xe2x80x9c3xe2x80x9d rotated by "THgr"=7xcfx80/4 phases. Thus, a demodulated frame synchronizing signal has eight phase states. Therefore, even when a frame-synchronizing signal is demodulated in any phase, the signal must be acquired.
Therefore, the BPSK demapper section 3 is configured by BPSK demappers 30 to 37 corresponding to phase rotations of "THgr"=0 (m=0), "THgr"=7xcfx80/4 (m=1), "THgr"=2xcfx80/4 (m=2), "THgr"=3xcfx80/4 (m=3), "THgr"=4xcfx80/4 (m=4), "THgr"=5xcfx80/4 (m=5), "THgr"=6xcfx80/4 (m=6), and "THgr"=7xcfx80/4 (m=7).
FIG. 25B shows BPSK demapping corresponding to a case in which a symbol stream of a demodulated frame synchronizing signal rotates by "THgr"=xcfx80/4 and the bit (0) appears on the signal point arrangement xe2x80x9c1xe2x80x9d and the bit (1) appears on the signal point arrangement xe2x80x9c5xe2x80x9d. The BPSK judging borderline shown by the bold line in FIG. 25B rotates by xcfx80/4 counterclockwise from the BPSK judging borderline of the BPSK demapping shown by the bold line in FIG. 25A at the time of reception at the same phase as that of transmission side. By using the BPSK demapper (refer to symbol 31 in FIG. 27) for performing the BPSK demapping shown in FIG. 25B, it is possible to stably acquire a frame synchronizing signal whose phase is rotated by "THgr"=xcfx80/4. A bit stream BPSK-demapped by the BPSK demapper 31 serves as an output B1 of the BPSK demapper section 3 in FIG. 24.
Similarly, the BPSK demappers 32 to 37 perform BPSK demapping at BPSK judging borderlines rotated by 2xcfx80/4, 3xcfx80/4, . . . , and 7xcfx80/4 counterclockwise from the BPSK judging borderline for BPSK demapping shown by the bold line in FIG. 25A to stably acquire frame synchronizing signals phase-rotated by "THgr"=2xcfx80/4, 3xcfx80/4, . . . , and 7xcfx80/4. Bit streams BPSK-demapped by the BPSK demappers 32 to 37 serve as outputs B2 to B7 of the BPSK demapper section 3 in FIG. 24. The BPSK demapper 30 performs BPSK demapping at the BPSK judging borderline shown by the bold line for BPSK demapping in FIG. 25A to stably acquire a frame synchronizing signal of "THgr"=0. A bit stream BPSK-demapped by the BPSK demapper 30 serves as an output B0 of the BPSK demapper section 3 in FIG. 24.
Configurations of sync detecting circuits 41 to 47 are the same as the configuration of the sync detecting circuit 40. By using the sync detecting circuits 40 to 47, a frame synchronizing signal is acquired by one of the sync detecting circuits 40 to 47 independently of phase rotation of a base band signal due to a phase state of the reference carrier wave fc1 or fc2 regenerated by the carrier-wave regenerating circuit 10 of the demodulating circuit 1 and a high-potential SYNAn (n=integer of 0 to 7) is transmitted from a sync detecting circuit acquiring the frame synchronizing signal.
The SYNAn output from the sync detecting circuits 40 to 47 is input to the OR gate circuit 53 and a logical sum SYNA of the SNYAn is output from the OR gate circuit 53. The frame synchronizing circuit 5 judges that frame sync is effectuated when it is confirmed that a high potential of the SYNA is alternately repeatedly input every certain frame interval and outputs a frame synchronizing pulse FSYNC every frame cycle. The frame-synchronizing-signal generator 6 generates a bit stream (referred to as regenerated frame-synchronizing signals) same as a pattern SYNCPAT of frame-synchronizing signals acquired by the BPSK demapper 3, synch detecting circuits 40 to 47, and the frame-synchronizing circuit 5 in accordance with a frame-synchronizing pulse FSYNC output from the frame-synchronizing circuit 5.
The above described is a process until a frame-synchronizing signal is acquired from I and Q symbol stream data I(8) and Q(8) output from the demodulating circuit 1 by the frame-sync detecting/regenerating circuit 2 shown in FIG. 24 and a certain time later, a regenerated frame-synchronizing signal is output from the frame synchronizing-signal generator 6.
Then, a transmission-configuration identifying operation by the transmission-configuration identifying circuit 9 will be described below.
The transmission-configuration identifying circuit 9 receives bit streams B0 to B7 output by the BPSK demapper 3 of the frame-sync detecting/regenerating circuit 2, SYNA0 to SYNA7 output by the sync detecting circuits 40 to 47, and a frame-synchronizing pulse FSYNC output by the frame-synchronizing circuit 5. When the circuit 9 receives the frame-synchronizing pulse FSYNC, it captures a bit stream Bn of a system repeatedly kept at a high potential among SYNA0 to SYNA7, extracts the TMCC pattern in FIG. 11A by using a predetermined timing signal generated in accordance with the frame-synchronizing pulse FSYNC, decodes the pattern, and outputs a modulation-system identifying signal DM showing a modulation system on which the present I and Q base-band signals I and Q depend (refer to FIG. 11B).
Then, absolute-phase generation is described which is realized by obtaining the present received-signal-phase rotation angle from a signal point arrangement of an acquired frame-synchronizing signal and antiphase-rotating demodulated I and Q base-band signals I(8) and Q(8) in accordance with the obtained received-signal-phase rotation angle.
Each symbol of symbol streams of frame-synchronizing signals BPSK-demapped at the transmission side and demodulated into I and Q base-band signals I(8) and Q(8) by the demodulating circuit 1 is demapped to bit (0) or (1) by the BPSK demapper section 3. The phase difference between a symbol demapped to bit (0) and a symbol demapped to bit (1) is equal to 180xc2x0. Therefore, by rotating symbols to be demapped to bit (1) of a frame-synchronizing-signal portion of a received symbol stream by 180xc2x0, symbol streams to be all demapped to bit (0) are obtained.
Moreover, by obtaining the average value of a plurality of symbols of the symbol stream to be all demapped to bit (0), a received-signal-point arrangement for bit (0) of BPSK is obtained. Therefore, by obtaining the phase difference between an obtained received-signal point for bit (0) of BPSK and a signal point arrangement xe2x80x9c0xe2x80x9d demapped to bit (0) at the transmission side, assuming the phase difference as a received-signal-phase rotation angle "THgr" and applying phase rotation of xcex7=xe2x88x92"THgr" to all I and Q base-band signals, it is possible to generate absolute phases of I and Q base-band signals I(8) and Q(8).
As described above, the frame-synchronizing-signal generator 6 generates a bit stream same as the pattern SYNCPAT of an acquired frame-synchronizing pulse by receiving the frame-synchronizing pulse output from the frame-synchronizing circuit 5 and supplies the bit stream to the 0xc2x0/180xc2x0 phase-rotating circuit 83 of the received-signal-phase rotation angle detecting circuit 8 as a regenerated frame-synchronizing signal. The 0xc2x0/180xc2x0 phase-rotating circuit 83 rotates phases of I and Q base-band signals by 180xc2x0 when a bit in a bit stream of a supplied regenerated frame-synchronizing signal is bit (1) but the circuit 83 does not rotate the phases in the case of bit (0).
The timing of a bit stream of a regenerated frame-synchronizing signal transmitted from the frame-synchronizing-signal generator 6 and that of a symbol stream of a frame-synchronizing signal in I and Q symbol streams are made to coincide with each other by the delay circuits 81 and 82 at the input side of the 0xc2x0/180xc2x0 phase-rotating circuit 83. The delay circuits 81 and 82 open their output gates only while a frame-synchronizing-signal-interval signal is output from the frame-synchronizing-signal generator 6. Therefore, I and Q symbol streams DI(8) and DQ(8) of a frame-synchronizing-signal portion are output from the delay circuits 81 and 82. In case of the I and Q symbol streams DI(8) and DQ(8), a symbol portion corresponding to bit (1) in a bit stream of a regenerated frame-synchronizing signal is phase-rotated by 180xc2x0 in the 0xc2x0/180xc2x0 phase-rotating circuit 83 but a symbol portion corresponding to bit (0) is transmitted to the averaging circuits 85 and 86 as symbol streams VI(8) and VQ(8) without any phase rotation. The symbol streams VI(8) and VQ(8) serve as symbol streams at the time of receiving a signal BPSK-demapped at the transmission side because it is judged that 20 bits configuring a frame-synchronizing signal are all set to bit (0).
FIG. 28(A) shows a signal point arrangement of I and Q symbol streams I(8) and Q(8) of a frame-synchronizing signal at the time of being received at a received-signal-phase rotation angle of "THgr"=0 and FIG. 28(B) shows signal point arrangements of I and Q symbol streams VI(8) and VQ(8) after converted by the 0xc2x0/180xc2x0 phase-rotating circuit 83. The I and Q symbol streams VI(8) and VQ(8) are transmitted to the averaging circuits 85 and 86 and, for example, each quantization bit length of the streams is converted into approx. 16 to 18 bits, and thereafter, four frames (16xc3x974=64 symbols) of them are averaged and the average value of the four frames is output as AVI(8) and AVQ(8) according to the quantization bit length of original 8 bits. In this case, I and Q symbol streams VI(8) and VQ(8) are averaged so that a signal point arrangement can be stably obtained even if a slight phase change or amplitude fluctuation of a received base-band signal occurs due to deterioration of a received C/N.
A received-signal point [AVI(8), AVQ(8)] of a signal obtained by BPSK-mapping bit (1) can be obtained by the averaging circuits 85 and 86. Then, the received-signal point [AVI(8), AVQ(8)] is input to the phase judging circuit 87 comprising a ROM, a received-signal-phase rotation angle "THgr" is obtained in accordance with a received-signal phase-rotation-angle judging table on the AVI-AVQ phase plane shown in FIG. 29, and a three-bit phase-rotation-angle signal AR(3) of three bits (natural binary number) corresponding to "THgr" is output. xe2x80x9cR=0-7xe2x80x9d in FIG. 29 denotes a decimal notation of a phase-rotation-angle signal AR(3). For example, xe2x80x9c"THgr"=0xe2x80x9d denotes a received-signal-phase rotation angle obtained by judging a signal point Z=[AVI(8), AVQ(8)] shown in FIG. 29 in accordance with a received-signal-phase rotation angle judging table. Therefore, R=0 is obtained and (000) is transmitted as the received-signal-phase rotation angle signal AR(3). When a received-signal-phase rotation angle "THgr" is equal to xcfx80/4, R becomes equal to 1 and (001) is transmitted as the received-signal-phase rotation angle signal AR(3).
Absolute-phase generation is realized when the remapper 7 comprising a ROM receives the received-signal-phase rotation angle signal AR(3) and phase-rotates I and Q base-band signals I(8) and Q(8) in accordance with the received-signal-phase rotation angle signal AR(3).
Then, functions of the remapper 7 will be described below. The remapper 7 configures a phase conversion circuit for making a signal point arrangement of received I and Q base-band signals I(8) and Q(8) same as that of the transmission side. A received-signal-phase rotation angle "THgr" is calculated by the received-signal-phase rotation angle detecting circuit 8 and the received-signal-phase rotation angle signal AR(3) corresponding to the received-signal-phase rotation angle "THgr" is supplied to the remapper 7. In this case, the decimal notation R of the received-signal phase-rotation-angle signal AR(3) is an integer of 0 to 7 and the relation with the received-signal-phase rotation angle "THgr" is defined as shown by the following expression (1).
R="THgr"/(xcfx80/4)xe2x80x83xe2x80x83(1)
Where
"THgr"=mxc2x7(xcfx80/4)
m: integer of 0 to 7
Absolute phase generation for I and Q base-band signals can be realized by applying reverse rotation, that is, phase rotation of xe2x88x92"THgr" to the received-signal-phase rotation angle "THgr". Therefore, the remapper 7 rotates phases of input I and Q base-band signals I and Q by an angle xcex7(=xe2x88x92"THgr") in accordance with the following expressions (2) and (3) and outputs absolute-phase-generated I and Q base-band signals Ixe2x80x2(8) and Qxe2x80x2(8) (hereafter also referred to as Ixe2x80x2 and Qxe2x80x2 by omitting the number of quantization bits).
Ixe2x80x2=I cos(xcex7)xe2x88x92Q sin(xcex7)xe2x80x83xe2x80x83(2)
Qxe2x80x2=I sin(xcex7)+Q cos(xcex7)xe2x80x83xe2x80x83(3)
In case of the above conventional received-signal-phase rotation angle detecting circuit, however, when configuring the 0xc2x0/18xc2x0 phase-rotating circuit 83 through table conversion, the memory capacity requires 128 Kbytes (=216xc3x9716 bits). Moreover, when configuring a phase discriminating circuit 86 through table conversion, the memory capacity requires 216xc3x973 bits and thereby, a problem occurs that the circuit greatly increases in size.
It is an object of the present invention to provide an apparatus for generating an absolute phase of a signal received by a receiver requiring only a small circuit size.
The apparatus for generating an absolute phase of a signal received by a receiver according to claim 1 of the present invention uses a receiver comprising demodulating means for demodulating a signal to be PSK-modulated in which at least 8PSK-modulated digital signal among 8PSK-modulated digital signal, QPSK-modulated digital signal and a BPSK-modulated digital signal is time-multiplexed with a BPSK-modulated frame-synchronizing signal, by using carrier waves regenerated by carrier-wave regenerating means and outputting I and Q symbol-stream data; frame-synchronizing-signal acquiring means for acquiring a frame-synchronizing signal from the demodulated I and Q symbol-stream data; received-signal-phase rotation angle detecting means for detecting a phase rotation angle of I and Q symbol-stream data output from the demodulating means against the transmission side; and antiphase rotating means for antiphase-rotating a phase of I and Q symbol-stream data output from the demodulating means by a phase rotation angle detected by the received-signal-phase rotation angle detecting means so that the carrier-wave regenerating means of the demodulating means has a phase error table storing carrier-wave phase error data for various demodulated I and Q symbol-stream data sets for each modulation system, reads phase error data corresponding to the demodulated I and Q symbol-stream data from a phase error table of a corresponding modulation system while the demodulating means demodulates a certain modulation-system portion under normal reception, and corrects a phase of a carrier wave; characterized in that the received-signal phase-rotation-angle detecting means includes phase-error data reading means for reading high-order bits for judging whether the absolute value of a phase error is larger or smaller than (xcfx80/8)+sxc2x7(xcfx80/4) (s is 0 or 1) among phase error data corresponding to the demodulated I and Q symbol-stream data from a phase error table for BPSK modulation of the carrier-wave regenerating means and discriminating means for discriminating a phase rotation angle of a symbol portion corresponding to bit (0) (or bit (1)) of a frame-synchronizing signal against the transmission side in I and Q symbol-stream data output from demodulating means in accordance with the sign bit data of I (or Q) symbol-stream data of a portion corresponding to bit (0) (or bit (1)) of a frame-synchronizing signal acquired by the frame-synchronizing-signal acquiring means in demodulated I and Q symbol-stream data and phase error data read by the phase error data reading means correspondingly to the portion and outputting a discrimination result.
A received-signal-phase rotation angle is univocally determined in accordance with a high-order bit for judging whether the absolute value of a phase error in phase error data according to a phase error table for BPSK modulation corresponding to demodulated I and Q symbol-stream data is larger or smaller than (xcfx80/8)+sxc2x7(xcfx80/4) (s is 0 or 1) and sign bit data of I (or Q) symbol-stream data of a portion corresponding to bit (0) (or bit (1)) of a frame-synchronizing signal and can be identified through a simple operation. Therefore, it is unnecessary to use a large-scale ROM dedicated for discrimination of a phase rotation angle and thereby, it is possible to decrease a circuit size.
The apparatus for generating an absolute phase of a signal received by a receiver according to claim 2 of the present invention uses a receiver comprising demodulating means for demodulating a signal to be PSK-modulated in which at least 8PSK-modulated digital signal and a QPSK-modulated digital signal among 8PSK-modulated digital signal, QPSK-modulated digital signal, and BPSK-modulated digital signal are time-multiplexed with a BPSK-modulated frame-synchronizing signal, by using carrier waves regenerated by carrier-wave regenerating means and outputting I and Q symbol-stream data; frame-synchronizing-signal acquiring means for acquiring a frame-synchronizing signal from the demodulated I and Q symbol-stream data; received-signal-phase rotation angle detecting means for detecting a phase rotation angle of I and Q symbol-stream data output from the demodulating means against the transmission side; and antiphase rotating means for antiphase-rotating and outputting a phase of I and Q symbol-stream data output from the demodulating means by a phase rotation angle detected by the received-signal-phase rotation angle detecting means so that the carrier-wave regenerating means of the demodulating means has a phase error table storing carrier-wave phase error data for various demodulated I and Q symbol-stream data sets for each modulation system, reads phase error data corresponding to the demodulated I and Q symbol-stream data by referring to a phase error table of a corresponding modulation system while the demodulating means demodulates a certain modulation-system portion under normal reception, and corrects a phase of a carrier wave; characterized in that the received-signal-phase rotation angle detecting means includes phase-error data reading means for reading high-order bits for judging whether the absolute value of a phase error is larger or smaller than xcfx80/8 among phase error data corresponding to the demodulated I and Q symbol-stream data out of a phase error table for QPSK modulation of the carrier-wave regenerating means and discriminating means for discriminating a phase rotation angle of a symbol portion corresponding to bit (0) (or bit (1)) of a frame-synchronizing signal against the transmission side in I and Q symbol-stream data in accordance with the sign bit data of I and Q symbol-stream data of a portion corresponding to bit (0) (or bit (1)) of a frame-synchronizing signal acquired by the frame-synchronizing-signal acquiring means and phase error data read by the phase error data reading means correspondingly to the portion and outputting a discrimination result.
A received-signal-phase rotation angle is univocally determined in accordance with a high-order bit for judging whether the absolute value of a phase error in phase error data according to a phase error table for QPSK modulation corresponding to demodulated I and Q symbol-stream data is larger or smaller than xcfx80/8 and sign bit data of I and Q symbol-stream data of a portion corresponding to bit (0) (or bit (1)) of a frame-synchronizing signal and can be identified through a simple operation. Therefore, it is unnecessary to use a large-scale ROM dedicated to discrimination of a phase rotation angle and thereby, it is possible to decrease a circuit size.